Our student, Hasan Hassan, has won the "HiPEAC Paper Award" for the paper he published during his master's degree study. The paper was prepared with valuable contributions from Assoc. Prof. Oguz Ergin, his advisor and the head of Computer Engineering Department, and academics from Carnegie Mellon University, US. The paper, of which the details are available below, has been published in proceedings of "23rd International Symposium on High Performance Computer Architecture (HPCA)". HPCA is one of 3 major conferences in the field of computer architecture.


ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality

Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oğuz Ergin, Onur Mutlu

Abstract: DRAM latency continues to be a critical bottleneck for system performance. In this work, we develop a low-cost mechanism, called ChargeCache, that enables faster access to recently-accessed rows in DRAM, with no modifications to DRAM chips. Our mechanism is based on the key observation that a recently-accessed row has more charge and thus the following access to the same row can be performed faster. To exploit this observation, we propose to track the addresses of recently-accessed rows in a table in the memory controller. If a later DRAM request hits in that table, the memory controller uses lower timing parameters, leading to reduced DRAM latency. Row addresses are removed from the table after a specified duration to ensure rows that have leaked too much charge are not accessed with lower latency. We evaluate ChargeCache on a wide variety of workloads and show that it provides significant performance and energy benefits for both single-core and multi-core systems.


HiPEAC (European Network on High Performance and Embedded Architecture and Compilation) has been established to steer the research on high performance computing and embedded systems and encourage the collaboration between the academia and the industry in Europe.